In this paper, a photonic crystal structure composed of the silicon rods is proposed for an all-Optical 4*2 encoder. Four input ports are connected to two outputs port via the cross-connections. Different radii of rods as defects are placed in the cross-connection region for coupling the Optical waves from the input waveguides to the desired outputs. The total size of the device is about 133 μm2. Plane-wave expansion and finite difference time domain methods are used to calculate the band diagram and simulation of the Optical wave propagation inside the structure, respectively. The maximum rise time of the device for all possible states is just about 205 fs which is less than one in the previous works. No need to a bias port and using the same power at input ports are other advantages of this work. The normalized output power margins for logic 0 and 1 are calculated by 2% and 34%, respectively. The simulation results demonstrate the presented structure is capable of using in Optical integrated circuits.

Marine communication systems have always faced challenges such as signal attenuation, wave interference, and bandwidth limitations. The use of photonic crystals as a platform for implementing Optical encoders in communication systems has attracted the attention of researchers due to the unique features of these structures, such as precise light guiding and dispersion control. Optical encoders are circuits used in the design of Optical processors. To reduce the size of Optical devices, it is essential to design small-scale logic circuits. In this study, a 2×4 all-Optical encoder based on two-dimensional photonic crystals is designed and simulated. The simple structure of this Optical encoder enables its use in integrated Optical circuits. Due to its small-scale structure and the use of defect pathways, the encoder’s transmission delay is reduced, resulting in an increased data bit rate. The transmission delay obtained for this proposed encoder is less than 90 femtoseconds. Another feature of this proposed Optical encoder is that the Optical output power in the logic "0" state is very low, which increases the contrast ratio.

In this paper, we proposed an all Optical 4-to-2 encoder that has 4 input and 3 output ports. This device generates a 2 bit binary code based on which input port is active. We used nonlinear photonic crystal ring resonators along with Optical power splitter for realizing the proposed encoder. In this device the switching rate and area are obtained about 333 GHz and 612μ m2 respectively.

This paper deals with the design and simulation of all-Optical 4×2 encoder using the wave interference effect in photonic crystals. By producing 4 Optical waveguides as input and two waveguides as output, the given structure was designed. The size of the designed structure is 133. 9 μ m2. The given all-Optical encoder has a contrast ratio of 13. 2 dB, the response time of 0. 45 ps, and also the bit transfer rate of 2. 2 Tbit/s. The results from these structures suggest the high flexibility of the structures, their resolution rates, and appropriate response time relative to that of other structures in this rank as well as their applicability in terms of dividing. To elicit the Optical band gap rage for structure design, the plane wave expansion method and also the finite difference time domain methods were used to investigate the results from designed structures.

In this paper, in a unique work, the structure of NOT / XOR multifunctional all-Optical logic gates is provided using interference effects in 2D photonic crystal structures for use in photonic integrated circuits of next generation. The applicability of the structure has been analyzed by modifying the output waveguide to optimize it and finally examining its performance by placing several structures together for using in Optical integrated circuits. In both basic and optimized structures, the contrast ratio, response time, and data transfer rate were measured 36 dB, 0.176 ps and 5.68 Tbit/s, respectively. Appropriate output results along the very small size of about 75.78 µm2, these circuits make the logic very proper for use in Optical integrated circuits. For this purpose, in a more complete work, an all-optimal 4×2 encoder has been designed using optimized structure. In this structure, the contrast ratio is about 13.2 dB, the response time is 0.168 ps and the data transfer rate is 6 Tbit/s. The results of this NOT/XOR basic and optimized all-Optical logic gate structure as well as 4×2 encoder indicate the high flexibility and applicability of these designs for use in structures in this field for use in Optical integrated circuits. In this paper, the Plane Wave Expansion method is used to obtain and analyze the photonic band gap range and the Finite-difference time-domain is used to analyze and simulate the designed structures.

This paper presents a high-speed, low-power and low area encoder for implementation of flash ADCs. Key technique for design of this encoder is performed by convert the conventional 1-of-N thermometer code to 2-of-M codes (M = ¾ N). The proposed encoder is composed from two-stage; in the first stage, thermometer code are converted to 2-of-M codes by used 2-input AND and 4-input compound AND-OR gates. In the second stage by two ROM encoders, 2-of-M codes determine n-1 MSB bits and one LSB bit. The advantages of the proposed encoder rather than other similar works are high speed, low power consumption, low active area, and low latency with same bubble error removing capability. To demonstrate the mention specifications, 5-bit flash ADCs with conventional and proposed encoders in their encoder blocks, are simulated at 2-GS/s and 3. 5-GS/s sampling rates in 0. 18-μ m CMOS process. Simulation results show that the ENOB of flash ADCs with conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined almost 30-ps faster rather than the conventional encoder at 2-GS/s. Also, the power consumptions of the conventional and proposed encoders were 17. 94-mW and 11. 74-mW at 3. 5-GS/s sampling rate from a 1. 8-V supply, respectively. Corresponding, latencies of the conventional and proposed encoders were 3 and 2 clock cycles. In this case, number of TSPC D-FFs and logic gates of the proposed encoder is decreased almost 39% compared to the conventional encoder.

Nowadays, the use of hardware/software codesign has grown dramatically in the design of embedded systems since it can improve the processing power, system efficiency, and the total cost of production. In this method, some parts of the system are implemented in hardware and the other parts are implemented in software in order to satisfy the system constraints, including power consumption, area and processing time. This paper proposes a parallel architecture for motion estimation in HEVC encoder. In the proposed method, the motion estimation part of the encoder, which has a high computational complexity, is implemented in hardware, and the computational complexity of this part is improved using parallel processing. The hardware implementation of motion estimation part is much less complex than the adopted HM reference software, making it more suitable for embedded systems. Experimental results show a significant improvement over software implementation.

Web Application Firewall (WAF) is known as one of the Intrusion Detection System (IDS) solutions for protecting web servers from HTTP attacks. WAF is a tool to identify and prevent many types of attacks, such as XSS and SQL-injection. In this paper, deep machine learning algorithms are used for enriching the WAF based on the anomaly detection method. Firstly, we construct attributes from HTTP data, to do so we consider two models namely n-gram and one-hot. Then, according to Auto-encoder LSTM (AE-LSTM) as an unsupervised deep leaning method, we should extract informative features and then reduce them. Finally, we use ensemble isolation forest to train only normal data for the classifier. We apply the proposed model on CSIC 2010 and ECML/ PKDD 2007 datasets. The results show AE-LSTM has higher performance in terms of accuracy and generalization compared with naï ve methods on CSIC dataset; the proposed method also have acceptable detection rate on ECML/PKDD dataset using n-gram model.

Recent researches have determined that regularized auto-encoders can provide a good representation of data which improves the performance of data classification. These type of auto-encoders provides a representation of data that has some degree of sparsity and is robust against variation of data to extract useful information and reveal the underlying structure of data. The present study aimed to propose a novel approach to generate sparse, robust, and discriminative features through supervised regularized auto-encoders, in which unlike most existing auto-encoders, the data labels are used during feature extraction to improve discrimination of the representation and also, the sparsity ratio of the representation is completely adaptive with data distribution. Results reveal that this method has better performance in comparison to other regularized auto-encoders regarding data classification.